The memory cells of dynamic random access memories are comprised of two main components: a field-effect transistor and a capacitor. In DRAM cells utilizing a conventional planar capacitor (such as the one depicted in FIG. 1), far more chip surface area is dedicated to planar capacitor 11 than to field-effect transistor (FET) 12. Capacitor 11 has a lower plate formed from the n+ silicon substrate extension 13 of drain 14 of FET 12. Upper capacitor plate 15 is formed from a layer of n-type polycrystalline silicon. Substrate extension 13 is electrically insulated from upper plate 15 by an insulating layer 16. Planar capacitors have generally proven adequate for use in DRAM chips up to the one-megabit level. However, planar capacitors constructed with conventional dielectric materials appear to be unusable beyond the one-megabit DRAM level. As component density in memory chips has increased, the shrinkage of cell capacitor size has resulted in a number of problems. Firstly, the alpha-particle component of normal background radiation will generate electron-hole pairs in the n+ silicon substrate plate of a cell capacitor. This phenomena will cause the charge within the affected cell capacitor to rapidly dissipate, resulting in a "soft" error. Secondly, the sense-amp differential signal is reduced. This aggravates noise sensitivity and makes it more difficult to design a sense-amp having appropriate signal selectivity. Thirdly, as cell capacitor size is decreased, the cell refresh time must generally be shortened, thus requiring more frequent interruptions for refresh overhead. The difficult goal of a DRAM designer is therefore to increase or, at least, maintain cell capacitance as cell size shrinks, without resorting to processes that reduce product yield or that markedly increase the number of masking and deposition steps in the production process.
Several methods for providing adequate cell capacitance in the face of shrinking cell size are either in use or under investigation. Basically, the efforts fall into two categories. Efforts within the first category are aimed at creating complex three-dimensional capacitors; those within the second are aimed at improving the dielectric of the planar capacitor.
The three-dimensional technique currently receiving the most attention involves the creation of "trench" capacitors in the cell substrate. FIG. 2 depicts a DRAM cell having a typical trench capacitor 17. Similar in concept to planar capacitor 11 of FIG. 1, the trench is employed to provide greater plate area, and hence, greater capacitance. The lower plate 18 is still formed from n+ silicon substrate, while the upper plate 19 is formed from a layer of n-type polycrystalline silicon. Lower plate 18 and upper plate 19 are electrically insulated with a dielectric layer 20. DRAM chips employing trench capacitors have been built by a number of European, Japanese and U.S. companies, including Texas Instruments Inc., Nippon Electric Company, Toshiba, Matsuchita and Mitsubishi Electric Corporation. There are several problems inherent in the trench design, not the least of which is trench-to-trench capacitive charge leakage which is the result of a parasitic transistor effect between trenches. Another problem is the difficulty of completely cleaning the capacitor trenches during the fabrication process; failure to completely clean a trench will generally result in a defective cell.
Another three-dimensional technique, which is being used by Mitsubishi Electric Company, Hitachi, and Fujitsu Ltd., is the stacking of capacitor plates between dielectric layers on the DRAM cell surface. FIG. 3 is a graphic represenation of a typical DRAM cell having a stacked capacitor 21. Both the lower plate 22 and the upper plate 23 are made from n-type polycrystalline silicon layers and are separated by a dielectric layer 24. Lower plate 22 and upper plate 23 are both stacked on top of FET 12 and interconnect word line 25, resulting in a high-profile cell which requires more stringent process control for the connection of bit line 26 to FET source 27. The capacitor thus formed also fails to use the n+ silicon substrate extension 13 of FET drain 14 as a plate of capacitor 21. In this design, lower plate 22 is merely tied to substrate extension 13.
Alternatively, other schemes involve the use of ferroelectric materials for DRAM cell capacitor dielectrics. Since ferroelectric materials have a dielectric constant more than 100 times that of silicon oxides, the use of such materials has the potential for allowing the size of the DRAM-cell capacitor to be shrunk to one of the smaller cell elements without resorting to three-dimensional structures. Critics of ferroelectric materials point out that such materials suffer from a "wearout" mechanism. In addition, they warn that there are many chemical incompatibilities with the other materials used in integrated circuit fabrication and that the layering of ferroelectric films within integrated circuit structures has not yet been done successfully.